1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to packaging of semiconductor devices.
2. Background Art
For optimization of form factor, performance, and manufacturing cost, it is often desirable to integrate the components of a power circuit, such as a half-bridge based DC-DC converter or buck converter, into a single compact package. Thus, several package designs, including quad flat no leads (QFN) packages, have been developed to integrate several transistors within a single compact package. To provide sufficient electrical performance for the reliable operation of high power semiconductor packages, it is crucial to ensure high current carrying capacity and low resistance between transistors within the package. Additionally, for long-term package reliability, it is essential to provide proper thermal dissipation.
It is known to use a conductive clip to provide a high performance interconnect between transistors and input/output terminals within a package. Additionally, by exposing the conductive clip to the outside of the package, enhanced thermal dissipation may be provided, for example by affixing a heat sink to the exposed area of the conductive clip.
Unfortunately, conventional assembly processes may result in the tilting of the conductive clip. More specifically, since the conductive clip is conventionally supported on a single side of the package, the conductive clip tends to tilt inwards or outwards from the package molding, thus incompletely exposing the conductive clip and reducing yield. While it is possible to support the conductive clip on multiple areas of the package to reduce the incidence of such tilting, such a design undesirably increases the package form factor and cost.
Thus, a cost-effective solution is needed to support the efficient design and operation of high power semiconductor packages with enhanced thermal dissipation and a compact form factor.